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2ED020I12-FI dual igbt driver ic power managment & drives final datasheet, september 2007 never stop thinking.
edition 2007-09-10 published by infineon technologies ag, am campeon 1-12, d-85579 neubiberg ? infineon 2007. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as warranted char- acteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies ag is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices, please contact your nearest infi- neon office in germany or our infineon representatives worldwide (see at http://www.infineon.com). warnings due to technical requirements components may contain dang erous substances. for information on the types in question, please contact your nearest infineon office. infineon components may only be used in life-support device s or systems with the express written approval of in- fineon, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that th e health of the user or other persons may be endangered. for questions on technology, delivery and prices, please contact the infineon offices in germany or the infineon companies and representatives worldwide: see our webpage at http://www.infineon.com/gatedriver 2ED020I12-FI revision history: 2007-09-10 final datasheet previous version: preliminary datasheet v3.2 2ED020I12-FI page subjects (major changes since last revision) 12 update operating range 21 update application advices
type ordering code package packaging 2ED020I12-FI sp0002-65782 pg-dso-18-2 tape&reel 2ED020I12-FI final data final datasheet 3 september 2007 pg-ds o-18-2 dual igbt driver ic 2ED020I12-FI product highlights ? fully operational to 1.2 kv power supply operating range from 14 to 18 v gate drive currents of +1 a / ?2 a matched propagation delay for both channels high dv/dt immunity low power consumption general purpose operational amplifier general purpose comparator features floating high side driver undervoltage lockout for both channels 3.3 v and 5 v ttl compatible inputs cmos schmitt-triggered inputs with pull-down non-inverting inputs interlocking inputs dedicated shutdown input with pull-up rohs compliant
high and low side driver 2ED020I12-FI overview final datasheet 4 september 2007 final data 1overview the 2ED020I12-FI is a high voltage, high speed power mosfet and igbt driver with interlocking high and low side referenced outputs. the floating high side driver may be supplied directly or by means of a bootstrap diode and capacitor. in addition to the logic input of each driver the 2ED020I12-FI is e quipped with a dedicated shutdown input. all logic inputs are compatible with 3.3 v and 5 v ttl. the output drivers feature a high pulse current buffer stage designed for mini mum driver cross-conduction. propagation delays are matched to simplify use in hi gh frequency applications. both drivers are designed to drive an n-channel power mosf et or igbt which operate up to 1.2 kv. in addition, a general purpose operational amplifier and a general purpose comparator are provided which may be used for instance for current measurem ent or overcurrent detection.
high and low side driver 2ED020I12-FI pin configuration and functionality final datasheet 5 september 2007 final data 2 pin configurati on and functionality 2.1 pin configuration vsh gndh op+ outl vsl p-dso-18-2 (300mil) n.c. op - opo cp+ 2ED020I12-FI gnd outh inl cpo inh gndh cp - sd gndl figure 1 pin configuration (top view) 2.2 pin definitions and functions pin symbol function 1 inh logic input for high side driver 2 inl logic input for low side driver 3 sd logic input for shutdown of both drivers 4 gnd common ground 5 cpo open collector output of general purpose comparator 6 cp? inverting input of general purpose comparator 7 cp+ non-inverting input of general purpose comparator 8 opo output of general purpose op table 1 pin description
high and low side driver 2ED020I12-FI pin configuration and functionality final datasheet 6 september 2007 final data 9 op? inverting input of general purpose op 10 op+ non-inverting input of general purpose op 11 gndl low side power ground 1) 12 outl low side gate driver output 13 vsl low side supply voltage 14 n.c. (not connected) 15 n.e. (not existing) 16 n.e. (not existing) 17 gndh high side (power) ground 18 vsh high side supply voltage 19 outh high side gate driver output 20 gndh high side (power) ground 1) please note : gndl has to be connected directly to gnd pin symbol function table 1 pin description (cont?d)
high and low side driver 2ED020I12-FI block diagram final datasheet 7 september 2007 final data 3 block diagram sd cpo inh input logic delay tx rx logic uvlo voltage supply high side uvlo voltage supply op opo op+ op - low side cp+ clt cp cp - inl v cc gnd vsh outh gndh outl gndl vsl figure 2 block diagram
high and low side driver 2ED020I12-FI functional description final datasheet 8 september 2007 final data 4 functional description 4.1 power supply the power supply of both sides, ?vsl? and ?vsh?, is monitored by an undervoltage lockout block (uvlo) which enables operation of the corresponding side when the supply voltage reaches the ?on? threshold. a fterwards the internal voltage reference and the biasing circuit are enabled. when the supply voltage (vsl, vsh) drops below the ?off? threshold, the circuit is disabled. 4.2 logic inputs the logic inputs inh, inl and sd are fed into schmitt-triggers with thresholds compatible to 3.3v and 5v ttl. when sd is enabled (low), inh and inl are disabled. if inh is high (while inl is low), outh is enabled and vice versa. however, if both signals are high, they are internally disabled until on e of them gets low again. this is due to the interlocking logic of the device. see figure 3 (section 4.7). 4.3 gate driver 2ED020I12-FI features two ha rd-switching gate drivers wit h n-channel output stages capable to source 1a and to sink 2a peak cu rrent. both drivers are equipped with active- low-clamping capability. furthermore, they feature a large ground bounce ruggedness in order to compensate ground bounces ca used by a turn-off of the driven igbt. 4.4 general purpose operational amplifier this general purpose operational amplifier can be applied for current measurement of the driven low-side igbt. it is dedicated for fast operation with a gain of at least 3. the op is equipped with a -0.1 to 2v input stag e and a rail-to-rail output stage which is capable to drive 5ma. 4.5 general purpose comparator the general purpose comparator can be applied for overcurrent detection of the low side igbt. a dedicated offset as well as a pull- up and pull-down resistor has been introduced to its inputs for security reasons. 4.6 coreless transformer (clt) in order to enable signal transmission across the isolation barrier between low-side and high-side driver, a transformer based on clt-te chnology is employed. signals, that are to be transmitted, are specially encoded by the transmitter and correspondingly restored by the receiver. in this way emi due to variations of gndh (dv gndh /dt) or the magnetic flux density (d /dt) can be suppresed.to compensate the additional propagation delay
high and low side driver 2ED020I12-FI functional description final datasheet 9 september 2007 final data of transmitter, level shifter and receiver, a ded icated propagation delay is introduced into the low-side driver. 4.7 diagrams inh inl /sd outh outl figure 3 input/output timing diagram
high and low side driver 2ED020I12-FI electrical parameters final datasheet 10 september 2007 final data 5 electrical parameters 5.1 absolute maximum ratings note: absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. unless otherwise noted all parameters refer to gnd. parameter symbol limit values unit remarks min. max. high side ground gndh ? 1200 1200 v high side supply voltage vsh ? 0.3 20 v 1) high side gate driver output outh ? 0.3 vsh + 0.3 v 1) low side ground gndl ? 0.3 5.3 v low side supply voltage vsl ? 0.3 20 v 2) low side gate driver output outl ? 0.3 vsl + 0.3 v 3) logic input voltages (inh, inl, sd ) v in ? 0.3 5.3 v op input voltages (op?, op+) v op ? 0.3 5.3 v 4) op output voltage v opo ? 0.3 5.3 v cp input voltages (cp?, cp+) v cp ? 0.3 5.3 v 4) cp output voltage v cpo ? 0.3 5.3 v cp output maximal sink current i cpo ? 5 ma high side ground, voltage transient dv gndh /dt ? 50 50 v/ns esd capability v esd ? 2 kv 5) human body model package power disipation @t a = 25c p d ? 1.4 w 6) thermal resistance (both chips active), junction to ambient r thja ? 90 k/w 7)
high and low side driver 2ED020I12-FI electrical parameters final datasheet 11 september 2007 final data 5.2 operating range note: within the operating range the ic o perates as described in the functional description. unless otherwise noted al l parameters refer to gnd. thermal resistance (high side chip), junction to ambient r thja(hs) ? 110 k/w 6) thermal resistance (low side chip), junction to ambient r thja(ls) ? 110 k/w 6) junction temperature t j ? 150 c storage temperature t s ? 55 150 c 1) with reference to high side ground gndh. 2) with respect to both gnd and gndl. 3) with respect to gndl. 4) please note the different specifications for the operating range (section 5.2). 5) according to eia/jesd22-a114-b (discharging a 100pf capacitor through a 1.5k ? series resistor). 6) considering rth(both chips active)=90k/w 7) device soldered to reference pcb without cooling area parameter symbol limit values unit remarks min. max. high side ground gndh ? 1200 1200 v high side supply voltage vsh 14 18 v 1) low side supply voltage vsl 14 18 v 2) logic input voltages (inh, inl, sd ) v in 0 5 v op input voltages (op?, op+) v op ? 0.1 2 v cp input voltages (cp?, cp+) v cp ? 0.1 2 v parameter symbol limit values unit remarks min. max.
high and low side driver 2ED020I12-FI electrical parameters final datasheet 12 september 2007 final data 5.3 electrical characteristics note: the electrical characteristics involve the spread of values guaranteed for the supply voltages, load and junction temper ature given below. typical values represent the median values, which are related to production processes. unless otherwise noted all voltages are gi ven with respect to ground (gnd). vsl = vsh ? gndh = 15 v, c l = 1 nf, t a = 25 c. positive currents are assumed to be flowing into pins. junction temperature t j ? 40 105 c industrial applications, useful lifetime 87600h junction temperature t j ? 40 125 c other applications, useful lifetime 15000h 1) with reference to high side ground gndh. 2) with respect to both gnd and gndl. voltage supply parameter symbol limit values unit test condition min. typ max. high side leakage current i gndh ? 0 ? a gndh = 1.2 kv gndl = 0 v high side quiescent supply current i vsh ? 2.4 3.2 ma vsh = 15 v 1) ? 2.3 3.2 ma vsh = 15 v 1) t j = 125 c high side undervoltage lockout, upper threshold v vsh 1) 10.9 12.2 13.5 v high side undervoltage lockout, lower threshold v vsh 1) ? 11.2 ? v high side undervoltage lockout hysteresis ? v vsh 0.7 1 1.3 v parameter symbol limit values unit remarks min. max.
high and low side driver 2ED020I12-FI electrical parameters final datasheet 13 september 2007 final data low side quiescent supply current i vsl ? 3.9 5.0 ma vsl = 15 v 3.9 5.5 ma vsl = 15 v t j = 125 c low side undervoltage lockout, upper threshold v vsl 10.7 12 13.3 v low side undervoltage lockout, lower threshold v vsl ? 11 ? v low side undervoltage lockout hysteresis v vsl 0.7 1 1.3 v logic inputs parameter symbol limit values unit test condition min. typ max. logic ?1? input voltages (inh, inl, sd ) v in 2 ? ? v logic ?0? input voltages (inh, inl, sd ) v in ? ? 0.8 v logic ?1? input currents (inh, inl) i in ? 40 55 a v in = 5 v logic ?0? input currents (inh, inl) i in ? 0 ? a v in = 0 v logic ?1? input currents ( sd ) i in ? 0 ? a v in = 5 v logic ?0? input currents ( sd ) i in ?60 ?40 ? a v in = 0 v 1) with reference to high side ground gndh. voltage supply (cont?d) parameter symbol limit values unit test condition min. typ max.
gate drivers parameter symbol limit values unit test condition min. typ max. high side high level output voltage v vsh ? v outh ? 1.4 1.7 v i outh = ?1ma v inh = 5v high side low level output voltage v 1) with reference to high side ground gndh. outh 1) ? ? 0.1 v i outh = 1ma v inh = 0v low side high level output voltage v vsl ? v outl ? 1.4 1.7 v i outl = ?1ma v inl = 5v low side low level output voltage v outl ? ? 0.1 v i outl = 1ma v inl = 0v output high peak current (outl, outh) i out ? ? ? 1 a v in = 5 v v out = 0 v output low peak current (outl, outh) i out 2 ? ? a v in = 0 v v out = 15 v high side active low clamping v outh 1) ? 2.6 3 v inh =0v, vsh open i outh =200ma ? 2.7 3.2 v inh =0v, vsh open i outh =200ma t j = 125 c low side active low clamping v outl ? 2.6 3 v inl =0v, vsl open i outl =200ma ? 2.7 3.2 v inl =0v, vsl open i outl =200ma t j = 125 c high and low side driver 2ED020I12-FI electrical parameters final datasheet 14 september 2007 final data dynamic characteristics parameter symbol limit values unit test condition min. typ max. turn-on propagation delay t on ? 85 105 ns gndh = 0 v 20% v out ? 95 120 ns gndh = 0 v 20% v out t j = 125 c
high and low side driver 2ED020I12-FI electrical parameters final datasheet 15 september 2007 final data turn-off propagation delay t off ? 85 115 ns 80% v out ? 100 130 ns 80% v out t j = 125 c shutdown propagation delay t sd ? 85 115 ns 80% v out ? 100 130 ns 80% v out t j = 125 c turn-on rise time t r ? 20 40 ns 20% to 80% v out ? 30 50 ns 20% to 80% v out t j = 125 c turn-off fall time t f ? 20 35 ns 80% to 20% v out ? 25 40 ns 80% to 20% v out t j = 125 c delay mismatch (high & low side turn-on/off) ? t ? 15 25 ns t j = 25c see figure 6 ? 15 30 ns t j = 125c see figure 6 minimum turn-on input (inh, inl) pulse width t pon ? 50 75 ns 1) ? 55 80 ns 1) t j = 125c minimum turn-off input (inh, inl) pulse width t poff ? 50 75 ns 1) ? 55 80 ns 1) t j = 125 c 1) inh-pulses shorter than the ?minimum turn-on(off) input pulse width? are prolonged to 50ns (see figure 7 ). inl- input doesnt have this feature. general purpose operat ional amplifier op parameter symbol limit values unit test condition min. typ max. op input offset voltage ? v in ?10 0 10 mv op input offset voltage drift v drift ? 15 ? v/k op input high currents (op?, op+) i in ? 0 0.2 a v in = 2 v dynamic characteristics (cont?d) parameter symbol limit values unit test condition min. typ max.
high and low side driver 2ED020I12-FI electrical parameters final datasheet 16 september 2007 final data op input low currents (op?, op+) i in ? 0.2 0 ? a v in = 0 v op high output voltage v opo 4.9 ? ? v v op? = 0 v v op+ = 2 v op low output voltage v opo ? ? 0.1 v v op? = 2 v v op+ = 0 v op output source current i opo ? ? ? 5 ma v op+ = 2 v v op? = 0 v v opo = 0 v op output sink current i opo 5 ? ? ma v op+ = 0 v v op? = 2 v v opo = 5 v op open loop gain a ol ? 120 ? db op gain-bandwidth product a x bw ? 20 ? mhz 1) op phase margin 2) ? 70 ? 1) 1) design value 2) due to inevitable parasitics a minimal gain of 3 is recommended general purpose comparator cp parameter symbol limit values unit test condition min. typ max. cp input offset voltage ? v in ?45 ?30 ?15 mv v cp+ = v cp- cp input high current i cp? ? 20 35 a v cp? = 5v cp input low current i cp+ ?35 ?20 ? a v cp+ = 0 v cp low output voltage v cpo ? ? 0.2 v v cp+ = 2 v i cpo = 1 ma cp output leakage current i cpo ? ? 5 a v cp+ = 0 v v cp? = 2 v v cpo = 5 v general purpose operationa l amplifier op (cont?d) parameter symbol limit values unit test condition min. typ max.
high and low side driver 2ED020I12-FI electrical parameters final datasheet 17 september 2007 final data cp switch-on delay t d ? 100 ? ns r cpo = 4.7k ? v res = 5v v cpo = 4v cp switch-off delay t d ? 300 ? ns r cpo = 4.7k ? v res = 5v v cpo = 1v general purpose comparator cp (cont?d) parameter symbol limit values unit test condition min. typ max.
high and low side driver 2ED020I12-FI package outline final datasheet 18 september 2007 final data 6 package outline note: dimensions are given in mm. 6.1 soldering profile the soldering profile qualified for 2ed020i12 -fi (according to the standard ipc/jedec j-std-020c) is moisture sensitivity level 3. the peak reflow temperature for its package (volume < 350 mm 3 ) is 260 +0/-5 c.
high and low side driver 2ED020I12-FI diagrams final datasheet 19 september 2007 final data 7 diagrams 2v 0.8v 80% 80% 20% 20% inh/l outh/l t r t f t on t off figure 4 switching time waveform definition /sd outh/l t sd 0.8v 80% figure 5 shutdown waveform definition
inl inh outl outh 2v 0.8v 2v 0.8v 80% 80% 20% 20% t offl t onh t offh t onl high and low side driver 2ED020I12-FI diagrams final datasheet 20 september 2007 final data t = max (|t onh - t offl | , |t offh - t onl |) figure 6 delay matching waveform definitions inh outh 50ns 50ns figure 7 short inh-pulses prolongation
high and low side driver 2ED020I12-FI application advices final datasheet 21 september 2007 final data 8 application advices 8.1 operational amplifier to minimize the current consumption when th e operational amplifier is not used, it is necessary to connect both inputs properly, e.g connect op+ to 5v and op- to 0v or vice versa. on the other hand, the operational amplifier cannot opera te with a follower configuration , i.e op- = opo. a minimum gain of 3 has to be used so that its output opo has a stable behaviour. 8.2 power supply a) the connection of a capacitor (>10nf) as close as possible to the supply pins vsh, vsl is recommended for avoiding that possible oscillations in the supply voltage can cause erroneous operation of the output dr iver stage. total value of capacitance connected to the supply terminals has to be determined by taking into account gatecharge, peak current, supply voltage and kind of power supply. b) if a bootstrap power supply for the high side driver is applied, a resistor of 10 ? minimum in series with the bootstrap diode is recommended.
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